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page 1 of 12 document no. doc-44014-3 www.psemi.com ?2014 peregrine semiconductor corp. all rights reserved. voltage control and esd rf1 v ctrl rf2 p out p1db p in product description the PE45140 is a harp? technology-enhanced rf power limiter designed for use in tactical and military communications receivers, land mobile radio and other high performance power limiting applications. this power limiter has symmetric rf ports that limit incident power up to 50w pulsed in both biased and unbiased conditions. it provides an extremely fast limiting response to undesired high power signals while delivering low insertion loss and high linearity under safe operating power levels. unlike traditional pin diode solutions the limiting threshold can be adjusted through a low current control voltage (v ctrl ), eliminating the need for external components such as dc blocking capacitors, rf choke inductors, and bias resistors. the PE45140 is manufactured on peregrine?s ultracmos ? process, a patented variation of silicon-on- insulator (soi) technology on a sapphire substrate. peregrine?s harp? technology enhancements deliver high linearity and excellent harmonics performance. it is an innovative feature of the ultracmos process, offering the performance of gaas with the economy and integration of conventional cmos. preliminary specification ultracmos ? power limiter 20 mhz?2 ghz figure 1. functional diagram PE45140 features ?? monolithic drop in solution with no external components required ?? adjustable power limiting threshold from +22 dbm to +32 dbm ?? max power handling ?? +47 dbm pulsed (50w) ?? +40 dbm cw (10w) ?? unbiased power limiting operation ?? fast response and recovery time of 1 ns ?? dual mode operation ?? power limiting mode ?? power reflecting mode ?? superior esd rating and esd protection ?? 8 kv hbm on rf pins to gnd figure 2. package type 12-lead 3x3 mm qfn doc-tbd preliminary specification
preliminary specification PE45140 page 2 of 12 document no. doc-44014-3 ultracmos ? rfic solutions ?2014 peregrine semiconductor corp. all rights reserved. table 1. electrical specifications @ +25c (z s = z l = 50? ), unless otherwise noted parameter condition min typ max unit operating frequency 20 2000 mhz power limiting mode insertion loss 20 mhz?1 ghz 1?2 ghz 0.20 0.60 0.45 1.00 db db return loss 20 mhz?1 ghz 16 db p1db / limiting threshold v ctrl = ?2.5v @ 915 mhz 32 dbm leakage power 1 v ctrl = ?2.5v @ 915 mhz v ctrl = ?0.5v @ 915 mhz 31.5 29 34 31.5 dbm dbm leakage power slope v ctrl = ?1.0v @ 915 mhz 0.4 db/db unbiased leakage power 1 v ctrl = 0v 23.5 27 dbm input ip2 v ctrl = ?2.5v @ 915 mhz 104 dbm input ip3 v ctrl = ?2.5v @ 915 mhz 64 dbm response / recovery time 1 ghz 1 ns leakage power 1 v ctrl = +2.5v @ 915 mhz ?1 4.5 dbm switching time 3 state change to 10% rf 390 s power reflecting mode 2 notes: 1. measured with +40 dbm cw applied at input. 2. this mode requires the control voltage to toggle betw een +2.5v and -2.5v. at +2.5v, the limiter equivalent circuit is a low impedance to ground, reflecting most of the incident power back to the source. 3. state change is v ctrl toggle from ?2.5v to +2.5v. preliminary specification
preliminary specification PE45140 page 3 of 12 document no. doc-44014-3 www.psemi.com ?2014 peregrine semiconductor corp. all rights reserved. figure 3. pin configuration (top view) table 2. pin descriptions pin no. pin name description 1, 3, 4, 6, 7, 9 gnd ground 2 rf1 rf port 1 5 v ctrl control 8 rf2 rf port 2 pad gnd exposed pad: ground for proper operation 11 v dd supply voltage 10, 12 n/c no connect v ctrl gnd gnd n/c v dd n/c table 3. operating ranges parameter symbol min typ max unit supply voltage v dd 2.5 3.3 v supply current i dd 1 ua control voltage power limiting mode power reflecting mode v ctrl ?2.5 ?2.5 ?0.5 +2.5 v v rf input power, cw 1 p max,cw 40 dbm rf input power, pulsed 2 p max,pulsed 47 dbm operating temperature range t op ?55 +85 c storage temperature range t st ?65 +150 c rf input power, unbiased 3 p max,unb 40 dbm operating junction temperature t j +270 c table 4. absolute maximum ratings exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. notes: 1. human body model (hbm, mil_std 883 method 3015.7) 2. machine model (jedec jesd22-a115) 3. charged device model (jedec jesd22-c101) parameter symbol min max unit supply voltage v dd -0.3 3.6 v control voltage power limiting mode power reflecting mode v ctrl ?3.3 3.6 v storage temperature range t st ?65 +150 c esd voltage hbm 1 all pins rf pins to gnd v esd,hbm 7 8 kv kv esd voltage mm 2 , all pins v esd,mm 200 v esd voltage cdm 5 , all pins v esd,cdm 1 kv notes: 1. cw, 100% duty cycle, in 10 min, 50 ? 2. pulsed, 0.1% duty cycle of 1 s pulse width in 10 min, 50 ? v ctrl = 0v or v ctrl pin left not connected preliminary specification
preliminary specification PE45140 page 4 of 12 document no. doc-44014-3 ultracmos ? rfic solutions ?2014 peregrine semiconductor corp. all rights reserved. latch-up avoidance unlike conventional cmos devices, ultracmos devices are immune to latch-up. electrostatic discharge (esd) precautions when handling this ultracmos device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified. moisture sensitivity level the moisture sensitivity level rating for the PE45140 in the 12-lead 3x3 mm qfn package is msl1. dual mode operation power limiting mode the PE45140 performs as a linear power limiter with adjustable p1db / limiting threshold. the p1db / limiting threshold can be adjusted by changing the control voltage between ?2.5v and ?0.5v. if unbiased, or if v ctrl = 0v, the PE45140 still offers power limiting protection. power reflecting mode power reflecting mode requires a power detector to sample the rf input power and a microcontroller to toggle the limiter control voltage between +2.5v and ?2.5v based on the system protection requirements. at +2.5v, the limiter impedance to ground is less than 1 ? and most of the incident power will be reflected back to the source. at ?2.5v, the device operates as in power limiting mode. preliminary specification
preliminary specification PE45140 page 5 of 12 document no. doc-44014-3 www.psemi.com ?2014 peregrine semiconductor corp. all rights reserved. thermal data when limiting high power rf signals, the junction temperature of the power limiter can rise significantly. special consideration needs to be made in the design of the pcb to properly dissipate the heat away from the part and maintain the +270c maximum junction temperature. it is recommended to use best design practices for high power qfn packages: multi-layer pcbs with thermal vias in a thermal pad soldered to the slug of the package. special care also needs to be made to alleviate solder voiding under the part. table 5. theta jc parameter min typ max unit theta jc 16 c/w preliminary specification
preliminary specification PE45140 page 6 of 12 document no. doc-44014-3 ultracmos ? rfic solutions ?2014 peregrine semiconductor corp. all rights reserved. figure 5. input return loss vs. temperature figure 6. output return loss vs. temperature figure 4. insertion loss vs. temperature typical performance data @ +25c (z s = z l = 50 ? ), unless otherwise noted preliminary specification
preliminary specification PE45140 page 7 of 12 document no. doc-44014-3 www.psemi.com ?2014 peregrine semiconductor corp. all rights reserved. figure 9. p1db vs. v ctrl over temperature figure 7. p out vs. p in over v ctrl figure 8. p out vs. p in over frequency @ v ctrl = ?0.7v figure 10. p out vs. p in over frequency @ v ctrl = ?1.5v \ 5 0 5 10 15 20 25 30 35 40 10 15 20 25 30 35 40 pout ? (dbm) pin ? (dbm) ?2.5v ?1.5v ?0.7v ?0.5v 0v 2.5v 0 5 10 15 20 25 30 35 10 15 20 25 30 35 40 pout ? (dbm) pin ? (dbm) ?0.7v ? @ ? 915 ? mhz ?0.7v ? @ ? 2 ? ghz 0 5 10 15 20 25 30 35 10 15 20 25 30 35 40 pout ? (dbm) pin ? (dbm) ?1.5v ? @ ? 915 ? mhz ?1.5v ? @ ? 2 ? ghz typical performance data @ +25c, 915 mhz (z s = z l = 50 ), unless otherwise noted 15 20 25 30 35 40 \ 2.5 \ 2 \ 1.5 \ 1 \ 0.5 p1db ? (dbm) v ctrl (v) p1db ? @ ? ?55c ? (dbm) p1db ? @ ? 25c ? (dbm) p1db ? @ ? 85c ? (dbm) preliminary specification
preliminary specification PE45140 page 8 of 12 document no. doc-44014-3 ultracmos ? rfic solutions ?2014 peregrine semiconductor corp. all rights reserved. figure 14. p1db, iip3, iip2, leakage power @ p max vs. v ctrl figure 11. iip3 / iip2 vs. v ctrl over temperature figure 12. iip3 / iip2 vs. p in over v ctrl 20 30 40 50 60 70 80 90 100 110 120 10 15 20 25 30 35 iip3 ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \ \ \ \ \ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? typical performance data @ +25c, 915 mhz (z s = z l = 50 ), unless otherwise noted 30 40 50 60 70 80 90 100 110 120 130 \ \ \ \ \ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure 14. leakage power @ p max vs. v ctrl over temperature \ \ \ \ \ \ \ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? preliminary specification
preliminary specification PE45140 page 9 of 12 document no. doc-44014-3 www.psemi.com ?2014 peregrine semiconductor corp. all rights reserved. evaluation kit the power limiter evk board was designed to ease customer evaluation of peregrine?s PE45140. the bi-directional rf input and output are connected to rf1 and rf2 port through a 50 ? transmission line via sma connectors j2 and j3. a through 50 ? transmission line is available via sma connectors j5 and j6. this transmission line can be used to estimate the loss of the pcb over the environmental conditions being evaluated. the 2-pin connectors j1 and j4 are connected to the external bias v dd and v ctrl , respectively. the board is constructed of a four metal layer material with a total thickness of 62 mils. the top rf layer is rodgers ro4350b material with a 6.6 mil rf core and er = 3.66. the middle layers provide ground for the transmission lines. the transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 13.5 mils, trace gaps of 10 mils, and metal thickness of 2.1 mils. figure 15. evaluation board layout prt-51452 preliminary specification
preliminary specification PE45140 page 10 of 12 document no. doc-44014-3 ultracmos ? rfic solutions ?2014 peregrine semiconductor corp. all rights reserved. 50 ohm 50 ohm 50 ohm thru j2 j3 r1 0ohm c3 dni r2 0ohm c4 dni 1 gnd 2 rf1 3 gnd 4 gnd 5 vctrl 6 gnd 7 gnd 8 rf2 9 gnd 10 n/c 11 vdd 12 n/c 13 dap u1 pe4514 0 1 1 2 2 j1 header2 1 1 2 2 j4 header2 j5 j6 c1 dni c2 dni vdd figure 16. evaluation board schematic doc-44027 caution: contains parts and assemblies susceptib le to damage by electrostatic discharge (esd) preliminary specification
preliminary specification PE45140 page 11 of 12 document no. doc-44014-3 www.psemi.com ?2014 peregrine semiconductor corp. all rights reserved. top view bottom view side view recommended land pattern a 0.10 c (2x) c 0.10 c 0.05 c seating plane b 0.10 c (2x) 0.10 c a b 0.05 c all features pin #1 corner 3.00 3.00 0.500.05 0.02 0.152 ref. 1.800.10 1.800.10 1.00 ref. 0.50 0.250.05 (x12) 0.300.05 (x12) (x8) 0.30 (x12) 0.70 (x12) 1.90 3.80 3.10 1.90 0.50 (x8) figure 17. package drawing 12-lead 3x3 mm qfn figure 18. top marking specifications doc-52193 45140 yyww zzzzz doc-51207 = pin 1 designator 45140 = five digit part number yyww = date code, last two digits of the year and work week zzzzz = five digits of the lot number preliminary specification
preliminary specification PE45140 page 12 of 12 document no. doc-44014-3 ultracmos ? rfic solutions ?2014 peregrine semiconductor corp. all rights reserved. advance information: the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify custom ers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracmos and utsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. peregr ine products are protected under one or more of the following u.s. patents: http://patents.psemi.com . sales contact and information for sales and contact information please visit www.psemi.com . table 6. ordering information order code description package shipping method PE45140a-x PE45140 power limiter green 12-lead 3x3 mm qfn 500 units / t&r ek45140-01 PE45140 evaluation ki t evaluation kit 1 / box figure 19. tape and reel drawing preliminary specification

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